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The P8xCE528 acknowledges interrupt requests from 7
rate generator mode. That external interrupt 2 is falling
sources as follows:
edge triggered. It shares the Timer 2 interrupt vector,
" INT0 external interrupt
interrupt enable and interrupt priority bits. If bit
" INT1 external interrupt
T2CON.3/EXEN2 = 1, a HIGH-to-LOW transition at pin
" Timer 0 internal counter
P1.1/T2EX sets the interrupt request flag T2CON.6/EXF2
and can be used to generate an external interrupt.
" Timer 1 internal counter
The I2C-bus interrupt is generated by SI in S1INT. This flag
" Timer 2 internal counter / EXF2 external interrupt
has to be cleared by software.
" I2C-bus serial I/O interrupt
All of the bits that generate interrupts can be set or cleared
" UART serial I/O port interrupt.
by software, with the same result as though they had been
The External Interrupts INT0 and INT1 can each be either
set or cleared by hardware, with the exception of the
level-activated or transition-activated, depending on bits
I2C-bus interrupt request flag SI, which cannot be set by
IT0 and IT1 in TCON SFR. The flags that actually generate
software. Thus, interrupts can be generated or pending
these interrupts are bits IE0 and IE1 in TCON. When an
interrupts can be cancelled in software.
external interrupt is generated, the corresponding request
flag is cleared by the hardware when the service routine is
SETTING OR CLEARING THE INTERRUPT ENABLE REGISTER
vectored to, only if the interrupt was transition-activated. If
Each interrupt source can be individually enabled or
the interrupt was level-activated then the interrupt request
disabled by setting or clearing a corresponding bit in the
flag remains set until the external interrupt pin INTX goes
interrupt enable SFR IE. All interrupt sources can also be
HIGH.
globally enabled or disabled by setting or clearing bit EA in
Consequently the external source has to hold the request
the IE register.
active until the requested interrupt is actually generated.
Then it has to deactivate the request before the interrupt
service routine is completed, or else another interrupt will
be generated. As these external interrupts are active LOW
a `wired-ORing` of several interrupt sources to one input
pin allows expansion.
The Timer 0 and Timer 1 Interrupts are generated by TF0
and TF1, which are set by a rollover in their respective
timer/counter register (except for Timer 0 in Mode 3 of the
serial interface). When a Timer interrupt is generated, the
flag that generated it is cleared by the on-chip hardware
when the service routine is vectored to.
September 1993 35
Philips Semiconductors Preliminary specification
8-bit microcontroller with EMC and
P8xCE528
FEEPROM
The polling cycle is repeated with every machine cycle,
INTERRUPT PRIORITY STRUCTURE
and the values polled are the values present at S5P2 of the
Each interrupt source can be assigned one of two priority
previous machine cycle. Note that if an interrupt flag is
levels. Interrupt priority levels are defined in the SFR IP.
active but is not being responded to because of one of the
above conditions, and if the flag is inactive when the
Interrupt priority levels are as follows:
blocking condition is removed, then the blocked interrupt
" logic 0 = low priority
will not be serviced. Thus, the fact that the interrupt flag
" logic 1 = high priority.
was once active but not serviced is not remembered.
Every polling cycle is new.
A low priority interrupt may be interrupted by a high priority
interrupt. A high priority interrupt cannot be interrupted by
The processor acknowledges an interrupt request by
any other interrupt source. If two requests of different
executing a hard-ware generated LCALL to the
priority occur simultaneously, the high priority request is
appropriate service routine. In some cases it also clears
serviced. If requests of the same priority are received
the flag which generated the interrupt, and in others it does
simultaneously, an internal polling sequence determines
not. It clears Timer 0, Timer 1, and external interrupt flags.
which request is serviced. Thus, within each priority level,
An external interrupt flag (IE0 or IE1) is cleared only if it
there is a second priority structure determined by the
was transition-activated. All other interrupt flags are not [ Pobierz całość w formacie PDF ]
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The P8xCE528 acknowledges interrupt requests from 7
rate generator mode. That external interrupt 2 is falling
sources as follows:
edge triggered. It shares the Timer 2 interrupt vector,
" INT0 external interrupt
interrupt enable and interrupt priority bits. If bit
" INT1 external interrupt
T2CON.3/EXEN2 = 1, a HIGH-to-LOW transition at pin
" Timer 0 internal counter
P1.1/T2EX sets the interrupt request flag T2CON.6/EXF2
and can be used to generate an external interrupt.
" Timer 1 internal counter
The I2C-bus interrupt is generated by SI in S1INT. This flag
" Timer 2 internal counter / EXF2 external interrupt
has to be cleared by software.
" I2C-bus serial I/O interrupt
All of the bits that generate interrupts can be set or cleared
" UART serial I/O port interrupt.
by software, with the same result as though they had been
The External Interrupts INT0 and INT1 can each be either
set or cleared by hardware, with the exception of the
level-activated or transition-activated, depending on bits
I2C-bus interrupt request flag SI, which cannot be set by
IT0 and IT1 in TCON SFR. The flags that actually generate
software. Thus, interrupts can be generated or pending
these interrupts are bits IE0 and IE1 in TCON. When an
interrupts can be cancelled in software.
external interrupt is generated, the corresponding request
flag is cleared by the hardware when the service routine is
SETTING OR CLEARING THE INTERRUPT ENABLE REGISTER
vectored to, only if the interrupt was transition-activated. If
Each interrupt source can be individually enabled or
the interrupt was level-activated then the interrupt request
disabled by setting or clearing a corresponding bit in the
flag remains set until the external interrupt pin INTX goes
interrupt enable SFR IE. All interrupt sources can also be
HIGH.
globally enabled or disabled by setting or clearing bit EA in
Consequently the external source has to hold the request
the IE register.
active until the requested interrupt is actually generated.
Then it has to deactivate the request before the interrupt
service routine is completed, or else another interrupt will
be generated. As these external interrupts are active LOW
a `wired-ORing` of several interrupt sources to one input
pin allows expansion.
The Timer 0 and Timer 1 Interrupts are generated by TF0
and TF1, which are set by a rollover in their respective
timer/counter register (except for Timer 0 in Mode 3 of the
serial interface). When a Timer interrupt is generated, the
flag that generated it is cleared by the on-chip hardware
when the service routine is vectored to.
September 1993 35
Philips Semiconductors Preliminary specification
8-bit microcontroller with EMC and
P8xCE528
FEEPROM
The polling cycle is repeated with every machine cycle,
INTERRUPT PRIORITY STRUCTURE
and the values polled are the values present at S5P2 of the
Each interrupt source can be assigned one of two priority
previous machine cycle. Note that if an interrupt flag is
levels. Interrupt priority levels are defined in the SFR IP.
active but is not being responded to because of one of the
above conditions, and if the flag is inactive when the
Interrupt priority levels are as follows:
blocking condition is removed, then the blocked interrupt
" logic 0 = low priority
will not be serviced. Thus, the fact that the interrupt flag
" logic 1 = high priority.
was once active but not serviced is not remembered.
Every polling cycle is new.
A low priority interrupt may be interrupted by a high priority
interrupt. A high priority interrupt cannot be interrupted by
The processor acknowledges an interrupt request by
any other interrupt source. If two requests of different
executing a hard-ware generated LCALL to the
priority occur simultaneously, the high priority request is
appropriate service routine. In some cases it also clears
serviced. If requests of the same priority are received
the flag which generated the interrupt, and in others it does
simultaneously, an internal polling sequence determines
not. It clears Timer 0, Timer 1, and external interrupt flags.
which request is serviced. Thus, within each priority level,
An external interrupt flag (IE0 or IE1) is cleared only if it
there is a second priority structure determined by the
was transition-activated. All other interrupt flags are not [ Pobierz całość w formacie PDF ]